Analog Devices Inc. HMC7043 Clock Buffers

Analog Devices HMC7043 high-performance clock buffers manage the distribution of ultra-low phase noise references in high-speed data converters configured using either parallel or serial (JESD204B) interfaces. Designed for multi-carrier LTE and GSM base stations, the 3.2GHz HMC7043 clock buffers include a wide array of distribution and clock management features. These features simplify baseband and radio card clock tree designs.

With 14 low-noise and configurable outputs, the HMC7043 clock buffers provide flexibility in interfacing the FPGA and ADC/DAC components in base transceiver station (BTS) systems. Each of the 14 channels features independent, flexible phase management. The RF SYNC feature deterministically synchronizes multiple HMC7043 clock buffers. This operation simplifies frame alignment between the components and ensures that all clock outputs start with the same edge. SPI-programmable power/performance adjustment ensures proper setup and holds times for the data converters.

The HMC7043 devices achieve <15fs rms jitter performance at 2457.6MHz to improve a high-speed data converter’s signal-to-noise ratio and dynamic range. The devices also have a very low noise floor of −155.2dBc/Hz at 983MHz to distribute frac-N LO signals with excellent spurious performance.


  • JEDEC JESD204B support
  • Low additive jitter: <15fs rms at 2457.6MHz (12kHz to 20MHz)
  • Very low noise floor: −155.2dBc/Hz at 983.04MHz
  • Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
    • Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200MHz
    • JESD204B-compatible system reference (SYSREF) pulses
    • 25ps analog and ½ clock input cycle digital delay
    • Independently programmable on each of 14 clock output channels
  • SPI-programmable adjustable noise floor vs. power consumption
    SYSREF valid interrupt to simplify JESD204B synchronization
  • Supports deterministic synchronization of multiple HMC7043 devices
  • RFSYNCIN pin or SPI-controlled SYNC trigger for output synchronization of JESD204B
  • GPIO alarm/status indicator to determine system health
  • Clock input to support up to 6GHz
  • 48-lead, 7mm × 7mm LFCSP package


  • JESD204B clock generation
  • Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
  • Data converter clocking
  • Phase array reference distribution
  • Microwave baseband cards

Block Diagram

Block Diagram - Analog Devices Inc. HMC7043 Clock Buffers
Published: 2016-08-08 | Updated: 2022-03-11