The AD9554 clock's high level of integration, adaptive clocking capability, and OTN mapping algorithm embedded in DPLL, can reduce system costs by simplifying clocking circuitry and eliminating software control routines. Output jitter is 250fs over the 50kHz to 80MHz range and 350fs over the 12kHz to 20MHz range. The four analog-digital phase-locked loops (ADPLL) allow for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed. AD9554 operates over an industrial temperature range of −40°C to +85°C and is ideal for network synchronization, cleanup of reference clock jitter, SONET/SDH clocks up to OC-192, including FEC, Stratum 3 holdover, jitter cleanup, and phase transient control, cable infrastructure, and data communications.