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Altera Quartus® Prime Design Software

Altera Quartus® Prime Design Software delivers improvements across the three key areas designers care about most performance, productivity, and usability. It supports the latest Agilex™ 7 and Agilex 5 FPGA and SoC families, ensuring a seamless development experience for cutting-edge applications. Coming in an upcoming release, support for the new Agilex 3 FPGAs and SoCs family and new MAX 10 FPGA package options that squeeze 485 I/Os into a 19 x 19mm2 sized package. Fast compile times allow designers to accelerate FPGA development, with larger designs benefiting from even greater reductions. Enhanced compiler optimizations also significantly reduce peak virtual memory requirements, ensuring most FPGA designs compile within 64GB of memory. 

Features

  • Fast compile time:
    • Optimized synthesis and place-and-route algorithms reduce design compilation time, with larger designs benefiting the most
  • Extended no-cost IP licensing:
    • Includes Nios® V and other IPs, with auto-fetch capabilities for easy integration
  • Reduction in peak virtual memory usage:
    • Improved memory efficiency ensures most designs compile in less than 64GB of memory
  • Machine-learning-based estimation:
    • AI-driven post-synthesis area estimation improves design accuracy and optimization
  • Pre-compiled simulation libraries:
    • Expands pre-compiled components, reducing compile time and improving simulation efficiency
  • Enhanced embedded software development:
    • Improved toolsets and workflows for embedded software engineers
  • Board IP presets:
    • Predefined settings for interfaces like DisplayPort, PCIewith PIO, and HBM with NoC, streamlining system design
  • NoC visualization and cycle-accurate NoC simulation models:
    • Better representation of links, switches, and congestion for optimized Network-on-Chip (NoC) designs

Applications

  • Design Assistant:
    • Provides real-time design-rule checking to help close timing fast and improve overall design quality
  • Quartus exploration dashboard:
    • Visualization and debugging tools for better project insights
  • Design space exploration:
    • Tools to evaluate multiple design configurations and optimize for power, performance, and resource usage
  • Available in Docker containers:
    • Enables flexible development environments with cloud-based FPGA compilation support
  • Nios® V Processor:
    • Altera’s enhanced RISC-V-based soft processor with improved performance, reduced resource utilization, and new architectural features
  • Advanced link analyzer:
    • Updated support for F-Tile FHT and FGT transceivers, along with an enhanced platform/simulation engine
  • Partial Reconfiguration (PR):
    • Dynamically update sections of an FPGA while the rest of the design continues to function
  • Signal tap logic analyzer:
    • Embedded debugging tool for real-time signal monitoring and in-system verification

Software Features

  • Agilex™ 5 FPGA E-Series unleashed in Quartus Prime Pro 24.1
    • Harness the power of Agilex 5 FPGA E-Series with the Quartus Prime Pro 24.1, offered at no cost
    • Seamlessly progress from compile through bitstream generation for all Agilex 5 FPGA E-Series devices within the Quartus environment
    • Simply download a complimentary license to unlock the full potential of Agilex 5 FPGAs E-Series
  • Streamlined licensing for easy evaluation - discover the capabilities of Quartus with a 30-day evaluation license, enabling full bitstream generation
  • Revamped Quartus Prime installer for effortless setup
    • Enjoy offline installation directly from downloaded files, eliminating the need for constant internet access
    • Seamlessly update existing installations directly from the installer interface
    • Conveniently delete downloaded files post-installation for a clutter-free experience
  • Quartus Exploration Dashboard (preproduction) - dive deep into project coordination and visualize compilation results across multiple instances of Quartus Prime software
  • Launch simulations directly from the Quartus Prime GUI with a simple click
  • Next-level compilation features with Precompiled Components (PCC) - accelerate synthesis compile time with the innovative Precompiled Component (PCC) generation flow
  • Synthesis capabilities
    • Seamlessly transition older RTL files to conform to Verilog/VHDL standards with the RTL linter tool
    • Empower designs with improved RAM inference and the ability to suppress warnings in RTL modules
  • Enhanced timing analyzer functionality
    • Unlock scripting options and sign-off capabilities for advanced timing analysis
    • Visualize async CDCs and timing in Chip Planner
  • Advanced link analyzer features and enhancements
    • Link Builder
      • Intuitive UI for automatic channel/device import and schematic creation
      • Automatic link establishment with multi-lane S-parameter support for enhanced signal path management
    • Enjoy enhanced GUI scaling with high DPI monitor support for improved user experience
    • Enhanced Data Viewer to improve FEC code word error analysis results
  • Simulation time improvements
    • Intuitive UI for automatic channel/device import and schematic faster simulation times with the Qrun and FEC models
    • Fixes to reset sequencing, PLL lock timing, and bypassing of AVMM traffic across AIB
  • Comprehensive portfolio of IP solutions for Agilex 5 FPGA E-Series
    • MIPI D-PHY and MIPI CSI-2 support up to 2.5G
    • Transceiver direct PHY support up to 17G with transceiver toolkit enabled with Multi-Rate IP (MRIP) for implementing multiple protocols with varying data rates
    • Offers both DDR5 and LPDDR5
    • PCI Express Gen4 x4 enabled with scalable DMA IP
    • Ethernet 10G/25G with MAC and PCS capability and PTP 1588 support
    • JESD204C up to 17G
    • Unlock scripting options and sign-off capabilities for advanced timing analysis
    • Visualize async CDCs and timing in Chip Planner
    • Simulation time improvement
  • Agilex 7 IP
    • R-Tile
      • Multi-channel DMA IP (AXI) up to Gen5 x16
      • Transaction Layer (TL) Bypass Mode for flexibility integrating 3rd party PCIe Switch IP
      • Design example for Gen5 x4 endpoint configuration
    • F-Tile
      • Up to 2X simulation time reduction in PIPE mode with FastSIM along with Ubuntu driver support for all example designs
      • Extended support up to 64x embedded endpoint devices
      • Added Debug Tool Kit (DTK) on switch IP for expanded coverage

Quartus Prime software introduces concurrent analysis support, enabling designers to analyze results timing, netlist views, and compilation reports while compilation is still running. Partial Reconfiguration (PR) allows dynamic updates to sections of the FPGA; at the same time the rest of the design continues to function, and the Design Assistant helps catch potential design issues early by providing real-time guidance and recommendations, improving overall design quality and efficiency.

Additionally, designers can leverage cloud-based Quartus' FPGA programming tools, available in Dockers containers, for high-performance application acceleration in a cloud computing environment.

QUARTUS® PRIME PRO EDITION SOFTWARE, Version 24.1

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The Intel® Quartus® Prime Pro Edition Design Software, Version 24.1 includes functional and security updates. Users should keep the software up-to-date and follow the technical recommendations to help improve security. Additional security updates are planned and will be provided as they become available. Users should promptly install the latest version upon release. The software is optimized to support the advanced features in next-generation FPGAs and SoCs with the Intel Agilex® FPGA portfolio, Intel Stratix® 10 devices, Intel Arria® 10 devices, and Intel Cyclone® 10GX devices.

Features

  • Questa-Intel® FPGA Edition simulation tools
  • Add-ons
    • Intel FPGA power and thermal calculator
    • Intel FPGA AI Suite
  • Additional development tools
    • Intel Advanced Link Analyzer tool
    • Intel HLS compiler
    • DSP Builder for Intel FPGAs
    • Nios® II Embedded Design Suite
    • Intel SoC FPGA Embedded Development Suite
  • Embedded tools
    • Nios V and Nios II processor
    • Arm® Development Studio for Intel SoC FPGA
    • Ashling RiscFree IDE for Intel FPGAs
    • Intel Simics Simulator or Intel FPGAs
  • Design flow
    • Platform Designer - a system integration tool in the Quartus Prime Software that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems, saving significant time and effort in the FPGA design process
    • Block-Based Design - design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device
    • Partial Reconfiguration - reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function
  • Design entry/planning
    • Design Partition Planner - defining a design partition allows users to optimize and lock down the compilation results for individual blocks
    • Chip Planner - simplifies floorplanning by allowing users to view and constrain design logic within a visual display of the FPGA chip resources, use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter
    • Interface Planner - explores a device’s peripheral architecture and efficiently assigns interfaces, prevents illegal pin assignments by performing fitter and legality checks in real-time
    • Logic Lock Regions - a powerful type of logic placement and routing constraint, define any arbitrary region of physical resources on the target device as a Logic Lock region and then assign design nodes and other properties to the region
    • Multiprocessor Support (faster compile time) - results in faster compile times depending on the number of cores used
    • IP Base Suite - Intel provides full production licenses for some of its popular intellectual property (IP) cores in the Altera® FPGA IP Base Suite, which is free with the Quartus® Prime Software and Quartus Prime Pro Edition Software
  • Placement and routing
    • Fitter (Place and Route) - performs design placement and routing, the Fitter determines the best placement and routing of logic in the target FPGA device
    • Register Retiming - balances the register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric
  • Timing and power verification
    • Timing Analyzer - powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology
    • Design Space Explorer II - allows users to find optimal project settings for resource, performance, or power optimization goals
    • Power Analysis - features include Early Power Estimators, Altera® FPGA Power and Thermal Calculator, and the Power Analyzer that gives users the ability to estimate power consumption
  • Simulation and debug
    • Signal Tap Logic Analyzer - captures and displays the real-time signal behavior in an FPGA design allowing users to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment
    • Transceiver Toolkit - uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time
    • Questa-Intel FPGA Edition Software - version of the Siemens EDA Questa Core software targeted for Altera® FPGA devices

QUARTUS® PRIME STANDARD EDITION SOFTWARE

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The Intel® Quartus® Prime Standard Edition Design Software, Version 23.1, includes functional and security updates. The Standard Edition lets users design FPGAs using whatever method is most convenient. It supports the development of complex systems through a suite of full-featured, high-level design tools that provide C-based, system-/IP-based, and model-based design entry. The software includes extensive support for Intel Arria 10 devices, Arria V FPGAs, Arria V GZ FPGAs, Arria II FPGAs, Intel MAX® 10 devices, MAX V CPLDs, MAX II CPLDs, Intel Cyclone 10 LP devices, Cyclone V devices, Cyclone IV FPGAs, Stratix V FPGAs, and Stratix IV FPGAs.

Features

  • Questa-Intel® FPGA Edition simulation tools
  • Additional development tools
    • Intel Advanced Link Analyzer tool
    • Intel HLS compiler
    • DSP Builder for Intel FPGAs
    • Nios® II Embedded Design Suite
    • Intel SoC FPGA Embedded Development Suite
  • Embedded tools
    • Nios V and Nios II processors
    • Arm® Development Studio for Intel SoC FPGA
    • Ashling RiscFree IDE for Intel FPGAs
  • Design flow
    • Platform Designer - a system integration tool in the Quartus Prime Software that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems, saving significant time and effort in the FPGA design process
    • Partial Reconfiguration - reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function
  • Design entry/planning
    • Design Partition Planner - defining a design partition allows users to optimize and lock down the compilation results for individual blocks
    • Chip Planner - simplifies floorplanning by allowing users to view and constrain design logic within a visual display of the FPGA chip resources, use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter
    • Logic Lock Regions - a powerful type of logic placement and routing constraint, define any arbitrary region of physical resources on the target device as a Logic Lock region and then assign design nodes and other properties to the region
    • Multiprocessor Support (faster compile time) - results in faster compile times depending on the number of cores used
    • IP Base Suite - Intel provides full production licenses for some of its popular intellectual property (IP) cores in the Altera® FPGA IP Base Suite, which is free with the Quartus® Prime Software and Quartus Prime Pro Edition Software
  • Placement and routing
    • Fitter (Place and Route) - performs design placement and routing, the Fitter determines the best placement and routing of logic in the target FPGA device
    • Register Retiming - balances the register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric
  • Timing and power verification
    • Timing Analyzer - powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology
    • Design Space Explorer II - allows users to find optimal project settings for resource, performance, or power optimization goals
    • Power Analysis - features include Early Power Estimators, Altera® FPGA Power and Thermal Calculator, and the Power Analyzer that gives users the ability to estimate power consumption
  • Simulation and debug
    • Signal Tap Logic Analyzer - captures and displays the real-time signal behavior in an FPGA design allowing users to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment
    • Transceiver Toolkit - uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time
    • Questa-Intel FPGA Edition Software - version of the Siemens EDA Questa Core software targeted for Altera® FPGA devices

QUARTUS PRIME LITE EDITION SOFTWARE

Download options

The Intel® Quartus® Prime Lite Edition Design Software, Version 23.1, includes functional and security updates. The Lite Edition software provides an ideal entry point to high-volume device families and is available as a free download with no license file required. The Lite edition supports Intel Cyclone 10 LP devices, Cyclone V devices, Cyclone IV FPGAs, Arria II FPGAs, Intel MAX 10 devices, MAX V CPLDs, and MAX II CPLDs.

Features

  • Questa-Intel® FPGA Edition simulation tools
  • Additional development tools
    • Intel HLS compiler
    • DSP Builder for Intel FPGAs
    • Nios® II Embedded Design Suite
    • Intel SoC FPGA Embedded Development Suite
  • Embedded tools
    • Nios V and Nios II processors
    • Ashling RiscFree IDE for Intel FPGAs
  • Design flow: Platform Designer - a system integration tool in the Quartus Prime Software that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems, saving significant time and effort in the FPGA design process
  • Design entry/planning
    • Chip Planner - simplifies floorplanning by allowing users to view and constrain design logic within a visual display of the FPGA chip resources, use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter
    • IP Base Suite - Intel provides full production licenses for some of its popular intellectual property (IP) cores in the Altera® FPGA IP Base Suite, which is free with the Quartus® Prime Software and Quartus Prime Pro Edition Software
  • Placement and routing: Fitter (place and route) - performs design placement and routing, the Fitter determines the best placement and routing of logic in the target FPGA device
  • Timing and power verification
    • Timing Analyzer - powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology
    • Design Space Explorer II - allows users to find optimal project settings for resource, performance, or power optimization goals
    • Power Analysis - features include Early Power Estimators, Altera® FPGA Power and Thermal Calculator, and the Power Analyzer that gives users the ability to estimate power consumption
  • Simulation and debug
    • Signal Tap Logic Analyzer - captures and displays the real-time signal behavior in an FPGA design allowing users to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment
    • Questa-Intel FPGA Edition Software - version of the Siemens EDA Questa Core software targeted for Altera® FPGA devices

Additional Resources

Associated Products

Altera DK-DEV-10M50-C MAX® 10 FPGA Development Kit

Includes a MAX® 10 development board, power adapter, and mini-B USB to USB cable.

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Altera DK-DEV-10M50F484-B MAX® 10 FPGA Evaluation Kit

Provides an easy-to-use platform for evaluating the MAX® 10 FPGA technology.

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Altera Stratix® FPGA Development Tools

Hardware solutions and tools to accelerate the FPGA design process.

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Altera Stratix® 10 TX Signal Integrity Development Kits

Complete design environment with hardware and software for developing Stratix 10 TX FPGA designs.

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Altera Cyclone® V FPGAs & SoCs

Cost-optimized performance family with a broad mix of features.

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Altera Agilex® 5 FPGA E-Series 065 B Modular Dev Kit

Delivers a comprehensive prototyping and reference platform design environment.

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Altera Agilex® 5 FPGA E-Series 065B Premium Dev Kit

Comes in a tabletop form factor, packed  with a robust set of features and connectors.

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Altera Agilex® 7 F-Series FPGA Dev Kit (2x F-Tile)

Comprehensive hardware development platform featuring the Agilex 7 FPGA F-Series with two F-tiles.

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Altera Agilex™ 7 FPGA I-Series Development Kits

Used for developing and testing cutting-edge designs.

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Development platform designed to streamline the creation of AI inference solutions on FPGAs.

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Published: 2012-11-14 | Updated: 2025-06-20