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Alliance Memory 2GB/4GB/8GB LPDDR4 SDRAM

Alliance Memory 2GB/4GB/8GB LPDDR4 SDRAM is organized as 1 or 2 channels per device, and the individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is a 16n prefetch architecture with an interface. It's designed to transfer two data words per clock cycle at the I/O pins. These devices offer fully synchronous operations referenced to rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

Features

  • Configuration:
    • x32 for 2-channels per device (AS4C64M32MD4, AS4C128M32MD4, AS4C256M32MD4)
    • x16 for 1-channel per device (AS4C128M16MD4, AS4C256M16MD4)
    • 8 internal banks per each channel
  • On-Chip ECC:
    • Single-bit error correction (per 64-bits), which will maximize reliability
    • Optional ERR output signal per channel, which indicates ECC event occurrence
    • ECC Register, which controls ECC function
  • Low-voltage Core and I/O Power Supplies:
    • VDD2 /VDDQ = 1.06-1.17V, VDD1 = 1.70-1.95V
  • Low Voltage Swing Terminated Logic (LVSTL) I/O Interface
  • Internal VREF and VREF Training
  • Dynamic ODT :
    • DQ ODT: VSSQ Termination
    • CA ODT: VSS Termination
  • Selectable output drive strength (DS)
  • Max. Clock Frequency: 1.6GHz (3.2Gbps for one channel)
  • 16-bit Pre-fetch DDR data bus
  • Single data rate (multiple cycles) command/address bus
  • Bidirectional/differential data strobe per byte of data (DQS, DQS)
  • DMI pin support for write data masking and DBI functionality
  • Programmable READ and WRITE latencies (RL/WL)
  • Programmable and on-the-fly burst lengths (BL =16, 32)
  • Support non-target DRAM ODT control
  • Directed per-bank refresh for concurrent bank operation and ease of command scheduling
  • ZQ Calibration
  • Operation Temperature:
    • Automotive A2 (TC = -40°C to 105°C）
  • On-chip temperature sensor to control self-refresh rate
  • On-chip temperature sensor whose status can be read from MR4
  • RoHS-compliant, "green" packaging
  • Package:
    • 2Gb/4Gb: 200 ball FBGA (10mm x 14.5mm x 0.8mm)
    • 8Gb: 200 ball FBGA (10mm x 14.5mm x 1.1mm)

Block Diagram

Alliance Memory 2GB/4GB/8GB LPDDR4 SDRAM
Alliance Memory 2GB/4GB/8GB LPDDR4 SDRAM
Published: 2020-12-08 | Updated: 2022-03-11